Capacitors are widely used in many integrated circuit semiconductor devices. For example, capacitors are used to store data in Dynamic Random Access Memory (DRAM) devices. As is well known to those having skill in the art, an integrated circuit capacitor includes a first, lower or bottom electrode, a second, top or upper electrode, and a dielectric layer therebetween.
As semiconductor devices become more highly integrated, the cell size of a DRAM may decrease along with the effective area of a lower electrode of a cell capacitor. However, a predetermined amount of cell capacitance may be desirable. In order to obtain a high cell capacitance in a small area, it may be desirable to employ a high-k dielectric layer, formed of a material such as Al2O3 or Al2O3/HfO2, which has several to several hundred times the dielectric constant of an oxide/nitride/oxide (ONO) layer that is conventionally used as a capacitor dielectric layer.
However, a doped polysilicon (poly-Si) electrode, which is conventionally used as a capacitor upper electrode or capacitor lower electrode, may react with a high-k dielectric layer and degrade the electrical characteristics of the capacitor. In order to reduce or prevent this problem, a low-k dielectric layer, such as a SiON layer, can be additionally coated between the doped poly-Si electrode and the high-k dielectric layer. In this case, however, the thickness of the capacitor dielectric layer may substantially increase.
In another method, one or both of the upper and lower electrodes of a capacitor using a high-k dielectric layer may be formed of a metal layer, which generally is less reactive than a poly-Si layer. The metal layer may be a metal or a conductive oxide or conductive nitride of a metal. In comparison with a semiconductor-insulator-semiconductor (SIS) capacitor including upper and lower electrodes formed of doped poly-Si, a capacitor including a metal upper electrode and a poly-Si lower electrode may be referred to as a metal-insulator-semiconductor (MIS) capacitor, and a capacitor including metal upper and lower electrodes may be referred to as a metal-insulator-metal (MIM) capacitor.
However, the metal upper electrode may not readily function as a resistor layer for delaying signals, due to its low resistivity. For this reason, a double layer formed by stacking a doped poly-Si layer on a metal layer may be used as an upper electrode. Here, the doped poly-Si layer may be formed by depositing an amorphous silicon (a-Si) layer using a low-pressure chemical vapor deposition (LPCVD) process and annealing the a-Si layer to activate the a-Si layer. However, the annealing process can lead to a higher leakage current than when the upper electrode is formed of only a metal layer.
FIG. 1 is a graph illustrating the higher leakage current due to annealing of an n-type doped poly-Si layer for activation in a conventional MIS capacitor. In FIG. 1, (a) denotes the leakage current of an MIS capacitor including an upper electrode formed of only a TiN layer, which was not annealed. Also in FIG. 1, (b) denotes the leakage current of an MIS capacitor including an upper electrode formed of a double layer obtained by stacking an n-type doped poly-Si layer on a TiN layer. The n-type doped poly-Si layer was deposited using an LPCVD process at a temperature of 530° C. and annealed in a furnace under an N2 atmosphere at a temperature of 600° C. for 30 minutes.
From FIG. 1, it can be seen that in case (b) where the annealing process for activation was performed, the leakage current and gate oxide thickness (Tox) were larger than those in case (a). Therefore, a low thermal budget process may be desired by changing the current annealing conditions of the n-type doped poly-Si layer where an annealing process is performed in a furnace at a temperature of 600° C. for 30 minutes or at a temperature 650° C. for 2 minutes. When fabricating a highly integrated DRAM cell, it may therefore be desirable to use only low-temperature processes after depositing a high-k dielectric layer, irrespective of the kind of electrode, to compensate for the poor thermal stability of the high-k dielectric layer and reduce the leakage current of a capacitor.